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Research Article
Design & Power Analysis of 8T SRAM Cell
E. Bharat Babu1
S. Raj Ganesh2
S. Arun3
M. Suseel Krishna4
1234Electronics & Communication Engineering, B.V. Raju Institute of Technology, Telangana, India.
Published Online: May-June 2022
Pages: 623-627
Cite this article
No DOIReferences
[1] Kevin Z. Embedded Memories for Nano-Scale VLSIs. Springer Publishing Company, Incorporated. 2009; 400.
[2] Brown AR, Roy G, Asenov A. Poly-Si-Gate- Related Variability in Decananometer MOSFETs with Conventional Architecture. Electron
Devices. IEEE Transactions in 2007; 54(11): 3056- 3063.
[3] Bo Z et al. A Sub-200mV 6T SRAM in 0.13um CMOS.in Solid-State Circuits Conference. ISSCC 2007. Digest of Technical Papers.
IEEE International. 2007.
[4] Cheng B, Roy S, Roy G, Brown A, Asenov A. Impact of Random Dopant Fluctuation on Bulk CMOS 6-T SRAM Scaling. In Solid-State
Device Research Conference. ESSDERC 2006.Proceeding of the 36th European. 2006.
[5] Singh J, Simon Hollis DKR, Mohanty SP. A single ended 6T SRAM cell design for ultra-low voltage applications. IEICE Electronics
Express 2008; 5(18): 750-755
[6] Mizuno H, Nagano T. Driving source-line cell architecture for sub-1-V high-speed low-power applications. Solid-State Circuits. IEEE
Journal of 1996; 31(4): 552-557.
[7] Takeda K. et al. A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications. Solid-State Circuits, IEEE
Journal of 2006; 41(1): 113-121.
[8] Chang L. et al. An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High Performance Caches. Solid-State Circuits,
IEEE Journal of 2008; 43(4): 956-963.
[9] Tae-Hyoung K. et al. A High-Density Subthreshold SRAM with Data-Independent Bit line Leakage and Virtual Ground Replica Scheme.In Solid-State Circuits Conference. ISSCC 2007. Digest of Technical Papers. IEEE International. 2007.
[10] Wang X, Roy S, Asenov A. Impact of Strain on the Performance of high k/metal replacement gate MOSFETs. Proc. 10th Ultimate
Integration on Silicon (ULIS 2009), 2009.
[2] Brown AR, Roy G, Asenov A. Poly-Si-Gate- Related Variability in Decananometer MOSFETs with Conventional Architecture. Electron
Devices. IEEE Transactions in 2007; 54(11): 3056- 3063.
[3] Bo Z et al. A Sub-200mV 6T SRAM in 0.13um CMOS.in Solid-State Circuits Conference. ISSCC 2007. Digest of Technical Papers.
IEEE International. 2007.
[4] Cheng B, Roy S, Roy G, Brown A, Asenov A. Impact of Random Dopant Fluctuation on Bulk CMOS 6-T SRAM Scaling. In Solid-State
Device Research Conference. ESSDERC 2006.Proceeding of the 36th European. 2006.
[5] Singh J, Simon Hollis DKR, Mohanty SP. A single ended 6T SRAM cell design for ultra-low voltage applications. IEICE Electronics
Express 2008; 5(18): 750-755
[6] Mizuno H, Nagano T. Driving source-line cell architecture for sub-1-V high-speed low-power applications. Solid-State Circuits. IEEE
Journal of 1996; 31(4): 552-557.
[7] Takeda K. et al. A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications. Solid-State Circuits, IEEE
Journal of 2006; 41(1): 113-121.
[8] Chang L. et al. An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High Performance Caches. Solid-State Circuits,
IEEE Journal of 2008; 43(4): 956-963.
[9] Tae-Hyoung K. et al. A High-Density Subthreshold SRAM with Data-Independent Bit line Leakage and Virtual Ground Replica Scheme.In Solid-State Circuits Conference. ISSCC 2007. Digest of Technical Papers. IEEE International. 2007.
[10] Wang X, Roy S, Asenov A. Impact of Strain on the Performance of high k/metal replacement gate MOSFETs. Proc. 10th Ultimate
Integration on Silicon (ULIS 2009), 2009.
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