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Research Article
High-Throughput Low-Latency Pipelined Divider for Single Precision Floating-Point Numbers
Nidish kumar P1
Abishek M2
Dineshkumar v3
123Electronics and communication engineering , Bannari Amman Institute of Technology, Tamil Nadu, India.
Published Online: March-April 2023
Pages: 218-223
Cite this article
No DOIReferences
1. S. Galal and M. Horowitz, “Energy-efficient floating-point unit design,” IEEE Trans. Comput., vol. 60, no. 7, pp. 913–922, Jul. 2011.
2. Y. Yang, Q. Yuan, and J. Liu, “An architecture of area-effective high radix floating-point divider with low-power consumption,”
IEEE Access, vol. 9, pp. 40039–40048, 2021.
3. P. Surapong and F. A. Samman, “Floating-point division operator based on CORDIC algorithm,” ECTI Trans. Comput. Inf.
Technol. (ECTI-CIT), vol. 7, no. 1, pp. 79–87, Jan. 1970.
4. K.-N. Han, A. F. Tenca, and D. Tran, “High-speed floating-point divider with reduced area,” Proc. SPIE Math. Signal Inf.
Process., vol. 7444, Oct. 2009, Art. no. 74440O.
5. P. Malik, “High throughput floating-point dividers implemented in FPGA,” in Proc. IEEE 18th Int. Symp. Design Diag.
Electron. Circuits Syst., Apr. 2015, pp. 291–294.1.
2. Y. Yang, Q. Yuan, and J. Liu, “An architecture of area-effective high radix floating-point divider with low-power consumption,”
IEEE Access, vol. 9, pp. 40039–40048, 2021.
3. P. Surapong and F. A. Samman, “Floating-point division operator based on CORDIC algorithm,” ECTI Trans. Comput. Inf.
Technol. (ECTI-CIT), vol. 7, no. 1, pp. 79–87, Jan. 1970.
4. K.-N. Han, A. F. Tenca, and D. Tran, “High-speed floating-point divider with reduced area,” Proc. SPIE Math. Signal Inf.
Process., vol. 7444, Oct. 2009, Art. no. 74440O.
5. P. Malik, “High throughput floating-point dividers implemented in FPGA,” in Proc. IEEE 18th Int. Symp. Design Diag.
Electron. Circuits Syst., Apr. 2015, pp. 291–294.1.
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