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Research Article
Novel Design of Ternary Arithmetic Circuits
B.Alekya Himabindu1
D.Sai Kumar2
G.Mahendra3
D.Madhu Srikanth4
K.Dinesh Reddy5
1Assistant Professor, Dept. of ECE, Santhiram Engineering College, Nandyal, Andhra Pradesh, India. 2345 Student, Dept. of ECE, Santhiram Engineering College, Nandyal, Andhra Pradesh, India.
Published Online: July-August 2022
Pages: 172-183
Cite this article
No DOIReferences
[1] P. S. Peercy, “The drive to miniaturization,” Nature, vol. 406, no. 6799, pp. 1023–1026, Aug. 2000.
[2] R. Ho, K. W. Mai, and M. A. Horowitz, “The future of wires,” Proc. IEEE, vol. 89, no. 4, pp. 490–504, Jul. 2001.
[3] G. Yeap, “Smart mobile SoCs driving the semiconductor industry: Technology trend, challenges and opportunities,” in IEDM
Tech.Dig., Dec. 2013. pp. 1.3.1–1.3.8.
[4] N. Magen, A. Kolodny, U. Weiser, and N. Shamir, “Interconnect-power dissipation in a microprocessor,” in Proc. Int. workshop Syst.
Level Interconnect Predict., 2004, pp. 7– 13.
[5] Y. Taur, “CMOS design near the limit of scaling,” IBM J. Res. Develop., vol. 46, no. 2.3,pp. 213–222, Mar. 2002.
[6] S. Iijima and T. Ichihashi, “Single-shell carbon nanotubes of 1-nm diameter,” Nature, vol.363, no. 6430, pp. 603–605, Jun. 1993.
[7] R. H. Baughman, “Carbon nanotubes—The route toward applications,” Science, vol. 297,no. 5582, pp. 787–792, Aug. 2002.
[8] V. Gaudet, “A survey and tutorial on contemporary aspects of multiple valued logic andits application to microelectronic circuits,”
IEEE J. Emerg. Sel. Topics Circuits Syst., vol.6, no. 1, pp. 5–12, Mar. 2016.
[9] M. Hurst, “Multiple-valued logic—Its status and its future,” IEEE Trans. Comput., vols.C–33, no. 12, pp. 1160–1179, Dec. 1984.
[10] K. C. Smith, “A multiple valued logic: A tutorial and appreciation,” Computer, vol. 21, no. 4, pp. 17–27, Apr. 1988.
[11] X. W. Wu and F. P. Prosser, “CMOS ternary logic circuits,” IEE Proc. G Circuits, DevicesSyst., vol. 137, no. 1, pp. 21–27, 1990.
[12] A. Raychowdhury and K. Roy, “Carbon-nanotube-based voltage-mode multiple-valued logic design,” IEEE Trans. Nanotechnol., vol.
4, no. 2, pp. 168–179, Mar. 2005.
[13] Y. Kang et al., “A novel ternary multiplier based on ternary CMOS compact model,” in Proc. IEEE 47th Int. Symp. Multiple-Valued
Log. (ISMVL), May 2017, pp. 25–30.
[2] R. Ho, K. W. Mai, and M. A. Horowitz, “The future of wires,” Proc. IEEE, vol. 89, no. 4, pp. 490–504, Jul. 2001.
[3] G. Yeap, “Smart mobile SoCs driving the semiconductor industry: Technology trend, challenges and opportunities,” in IEDM
Tech.Dig., Dec. 2013. pp. 1.3.1–1.3.8.
[4] N. Magen, A. Kolodny, U. Weiser, and N. Shamir, “Interconnect-power dissipation in a microprocessor,” in Proc. Int. workshop Syst.
Level Interconnect Predict., 2004, pp. 7– 13.
[5] Y. Taur, “CMOS design near the limit of scaling,” IBM J. Res. Develop., vol. 46, no. 2.3,pp. 213–222, Mar. 2002.
[6] S. Iijima and T. Ichihashi, “Single-shell carbon nanotubes of 1-nm diameter,” Nature, vol.363, no. 6430, pp. 603–605, Jun. 1993.
[7] R. H. Baughman, “Carbon nanotubes—The route toward applications,” Science, vol. 297,no. 5582, pp. 787–792, Aug. 2002.
[8] V. Gaudet, “A survey and tutorial on contemporary aspects of multiple valued logic andits application to microelectronic circuits,”
IEEE J. Emerg. Sel. Topics Circuits Syst., vol.6, no. 1, pp. 5–12, Mar. 2016.
[9] M. Hurst, “Multiple-valued logic—Its status and its future,” IEEE Trans. Comput., vols.C–33, no. 12, pp. 1160–1179, Dec. 1984.
[10] K. C. Smith, “A multiple valued logic: A tutorial and appreciation,” Computer, vol. 21, no. 4, pp. 17–27, Apr. 1988.
[11] X. W. Wu and F. P. Prosser, “CMOS ternary logic circuits,” IEE Proc. G Circuits, DevicesSyst., vol. 137, no. 1, pp. 21–27, 1990.
[12] A. Raychowdhury and K. Roy, “Carbon-nanotube-based voltage-mode multiple-valued logic design,” IEEE Trans. Nanotechnol., vol.
4, no. 2, pp. 168–179, Mar. 2005.
[13] Y. Kang et al., “A novel ternary multiplier based on ternary CMOS compact model,” in Proc. IEEE 47th Int. Symp. Multiple-Valued
Log. (ISMVL), May 2017, pp. 25–30.
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