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Abstract: This paper proposed the SRAM Architecture design using 8 Transistors to reduce the power leakages and improves the read & write delays. In the design the SRAM cell uses a charge sharing technique between the transistors to make SRAM more rigid against noises that occur due to low power supplies. Apart from noise reduction the read discharge power is reused. The circuit is also balanced with the same number of PMOS & NMOS, in order to achieve the maximum stability of SRAM. The comparison between standard 6T, 8T and proposed 8T with charges haring is made .Its hows that less power is consumed by 8T with charges haring than others.