Scheme of Squat Power, High Speed Fine Grain and Coarse Grain Twin Tail Comparator

Scheme of Squat Power, High Speed Fine Grain and Coarse Grain Twin Tail Comparator

AUTHOR

  • N JAYAPAL, N KARTHIKEYAN, P.N MANIMAGALAI
  • SUBMITTED

  • 2021
  • PUBLISHED MONTH

  • January-Feburary
  • ARTICLE TYPE

  • Research
  • DOWNLOAD

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    STATICS

    ABSTRACT


    Comparator is a fundamental building block in ADCs.
    Comparator is a device that compares two voltages or currents and
    gives a digital output that indicates which of the input is larger. In
    design of ADCs, comparators of low power consumption, high speed
    are used. In high speed analog to digital converters, comparator design
    has a crucial influence on the overall performance that can be
    achieved.
    In this paper, we have proposed a new low power, high speed
    single tail and double tail comparators using power gating techniques.
    The comparison of speed and power consumed by proposed fine grain
    and coarse grain double tail comparators with traditional comparators
    like single tail and double tail comparators is also presented.
    We observed that minimal propagation time delay and low
    power consumption is achieved by the proposed fine grain double tail
    comparators which make them suitable for high speed ADCs.
    Index Terms–Course Grain Double tail comparator, Fine Grain single
    tail comparator, Fine Grain Double tail comparator, dynamic clocked
    comparator, high speed analog to digital converters, low power analog
    design, switching transistor, preamplifier based comparators
    REFERENCES
    1. Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” Tata McGraw-Hill, Inc., 2002.
    2. HeungJun Jeon Yong-Bin Kim, “A CMOS Low-power Low-offset and High-speed Fully Dynamic Latched Comparator,” IEEE
    International SOC Conference, pp. 285, September 2010.
    3. Philip E. Allen and Douglas R. Holberg, “CMOS Analog Circuit Design,” 2nd Edition, Oxford University Press, First Indian
    Edition, 2010.
    4. T. Kobayashi, K. Nogami, T.Shirotori, and Y. Fujimoto, “A current controlled latch sense amplifier and a static power-saving input
    buffer for low-power architectures,” IEEE J. Solid-State Circuits, vol. 28, no. 4 pp. 523–527, Apr. 1993.
    5. M. Pelgrom, A. Duinmaijer, and A. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, no. 5

    pp. 1433–1440, Oct. 1989.

    Scheme of Squat Power, High Speed Fine Grain and Coarse Grain Twin Tail Comparator