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Research Article
Scheme of Squat Power, High Speed Fine Grain and Coarse Grain Twin Tail Comparator
N Jayapal1
N Karthikeyan2
P.N Manimagalai3
123Department of ECE, MEPCOSCHLENK Engineering College, TN, India.
Published Online: January-February 2021
Pages: 11-13
Cite this article
No DOIReferences
1. T. Kobayashi, K. Nogami, T.Shirotori, and Y. Fujimoto, “A current controlled latch sense amplifier and a static powersaving input buffer for low-power architectures,” IEEE J. Solid-State Circuits, vol. 28, no. 4 pp. 523–527, Apr.1993.
2. M. Pelgrom, A. Duinmaijer, and A. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, no. 5 pp. 1433–1440, Oct.1989.
3. S. Sheikhaei, S. Mirabbasi, and A. Ivanov, “A 0.35μm CMOS Comparator Circuit for High-Speed ADC Applications,” IEEE International Symposium on Circuits and Systems, pp. 6134-6137, May2005.
4. P.M. Figueiredo, Vital, J.C. “Low kickback noise techniques for CMOS latched comparators”, Circuits and Systems,2004.
5. H.P. Le, A. Zayegh and J. Singh , “Performance analysis of optimized CMOS comparator”, IEEE E. Letters, Vol. 39, Issue 11, pp. 833 – 835,2003.
2. M. Pelgrom, A. Duinmaijer, and A. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, no. 5 pp. 1433–1440, Oct.1989.
3. S. Sheikhaei, S. Mirabbasi, and A. Ivanov, “A 0.35μm CMOS Comparator Circuit for High-Speed ADC Applications,” IEEE International Symposium on Circuits and Systems, pp. 6134-6137, May2005.
4. P.M. Figueiredo, Vital, J.C. “Low kickback noise techniques for CMOS latched comparators”, Circuits and Systems,2004.
5. H.P. Le, A. Zayegh and J. Singh , “Performance analysis of optimized CMOS comparator”, IEEE E. Letters, Vol. 39, Issue 11, pp. 833 – 835,2003.
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